1. Field of the Invention
The present invention relates to a technique used for a memory storing data (user data) directly accessible to users, to reduce the capacity of a reserve storage area which does not directly stores the user data therein.
2. Description of the Background Art
In memories, generally, there also exist defective blocks and this hinders direct correspondence between logical addresses and physical addresses. For this reason, conventionally as to memories, known is a technique to provide a reserve storage area for storing information required for conversion between the logical addresses and the physical addresses.
As a method therefor, a reserve area is provided correspondingly to each data area (block) serving as a unit of access, to store characteristics information indicating whether the block is normal or defective therein. Then, at a predetermined timing (e.g., at power-on), a controller reads the characteristics information from all the reverse areas and makes a table indicating the correspondence between logical addresses and physical addresses. Alternatively, such a table may be held in a memory.
Further, a technique for suppressing the capacity of a reserve storage area required for the conversion between the logical addresses and the physical addresses without decreasing the access speed is disclosed in Patent Document 1 (Japanese Patent Application Laid Open Gazette No. 2008-204155).
In the technique of Patent Document 1, correlation between logical addresses and physical addresses is determined in such a manner as to associate the logical addresses in ascending order with the physical addresses in ascending order while skipping the physical addresses of defective blocks in a memory. Then, the physical addresses of the defective blocks are individually stored successively in ascending order into a plurality of second blocks in ascending order of the physical addresses thereof. In order to obtain a physical address from a logical address, a target block is searched for from the plurality of second blocks on the basis of the logical address and the physical address of the target block is added to the logical address.
In Patent Document 1, however, though the technique for the logical-physical conversion in a case where there exist initial defective blocks detected in a factory inspection is disclosed, no reference is made to the logical-physical conversion in a case where any defect occurs late in the memory during the use of the memory system.
Further, it is not desirable that the correspondence for logical-physical conversion should be changed over a lot of blocks when there occurs a late defective block (a defective block which occurs late).